1. Field of the Invention
The present invention generally relates to the field of automated packaging systems. More particularly, the present invention relates to the field adhesive backed carrier tape packaging systems utilizing a solid pressure sensitive adhesive (PSA) tape.
2. Description of the Prior Art
The following thirteen (13) prior art patents are found to be pertinent to the field of the present invention:
1. U.S. Pat. No. 2,885,849 issued to Wohlman, J R on May 12, 1959 for "Semiconductor Taping Apparatus" (hereafter the "Wohlman Patent"); PA1 2. U.S. Pat. No. 3,177,629 issued to Anspach on Apr. 13, 1965 for "Apparatus for Loading Components" (hereafter the "Anspach Patent"); PA1 3. U.S. Pat. No. 3,608,711 issued to Wiesler et al. on Sep. 28, 1971 for "Package for Electronic Devices and the Like". (hereafter the "'711 Wiesler Patent"); PA1 4. U.S. Pat. No. 3,691,436 issued to Maijers et al. on Sep. 12, 1972 for "Electrical Circuit Element having a Diagonal Abutment Strip and Method of Manufacturing the Same" (hereafter the "Maijers Patent"); PA1 5. U.S. Pat. No. 3,785,507 issued to Wiesler et al. on Jan. 15, 1974 for "Die Sorting System" (hereafter the "'507 Wiesler Patent"); PA1 6. U.S. Pat. No. 3,881,245 issued to Dudley et al. on May 6, 1975 for "Mounting Electrical Components On Thick Film Printed Circuit Elements" (hereafter the "Dudley Patent"); PA1 7. U.S. Pat. No. 3,971,193 issued to Tardiff et al. on Jul. 27, 1976 for "Machines For Sequencing Diverse Components" (hereafter the "Tardiff Patent"); PA1 8. U.S. Pat. No. 4,298,120 issued to Kaneko et al. on Nov. 3, 1981 for "Chip-Like Electronic Component Series And Method For Supplying Chip-Like Electronic Components" (hereafter the "Kaneko Patent"); PA1 9. U.S. Pat. No. 4,340,774 issued to Nilsson et al. on Jul. 20, 1982 for "Device For Mounting Circuit Components On A Circuit Board" (hereafter the "Nilsson Patent"); PA1 10. U.S. Pat. No. 4,575,995 issued to Tabuchi et al. on Mar. 18, 1986 for "Automatic Producing Apparatus Of Chip-Form Electronic Parts Aggregate" (hereafter the "Tabuchi Patent"); PA1 11. U.S. Pat. No. 4,724,954 issued to Sillner on Feb. 16, 1988 for "System For Conveying And Guiding Components, In Particular Electrical Construction Elements Which Are Held On A Belt In A Radially Or Quasi-Radially Belted Manner" (hereafter the "Sillner Patent"); PA1 12. U.S. Pat. No. 4,954,207 issued to Higuchi et al. on Sep. 4, 1990 for "Apparatus For Automatically Taping Electronic Components" (hereafter the "Higuchi Patent"); and PA1 13. U.S. Pat. No. 5,203,143 issued to Gutentag on Apr. 20, 1993 for "Multiple And Split Pressure Sensitive Adhesive Stratums For Carrier Tape Packaging System" (hereafter the "'143 Patent").
The Wohlman Patent discloses a semiconductor taping apparatus. The semiconductors are taped at lateral ends by a pair of first tapes, and another pair of second tapes where the adhesives in the first tapes face the adhesive side of the tapes in the pair of second tapes.
The Anspach Patent discloses an apparatus for loading components. These components are primarily larger components and also are primarily leaded diodes. A gap is provided in the carrier where the heads of the transistors are placed, but the transistors themselves are carried by having the lead sandwiched between the carrier tape and an adhesive tape.
The '711 Wiesler Patent discloses a package for electronic devices and the like, which utilizes a tape with a plurality of openings to receive a device. The device is held in place by an adhesive tape applied from the back, which is exposed at the opening and serves as a tape stratum for holding the device in place.
The Maijers Patent discloses an electrical circuit element having a diagonal abutment strip and method of manufacturing the same. In the Maijers Patent, small discrete components are interconnected by means of a strip of tape.
The '507 Wiesler Patent discloses a die sorting system which uses a strip comprised of a relatively narrow strip formed with indexing holes along one edge, and storage holes near the outer edge of the strip. On the bottom side, a thin pressure sensitive adhesive tape is laminated to the strip and provides an adhesive floor to hold the die at the bottom of the storage holes.
The Dudley Patent discloses a device for mounting electrical components on thick film printed circuit elements. Two metal strips are attached to printed areas and adhered by electrical resistance welding for contacting electrodes.
The Tardiff Patent discloses machines for sequencing diverse components. In the Tardiff Patent, small electrical components are sequenced and interconnected with tape at opposite ends of their lead portions.
The Kaneko Patent discloses a chip-like electronic component series and method for supplying chip-like electroniccomponents. It coomprises a tape-like member formed with a plurality of apertures with upper and lower cover sheets that contain small chip-like electronic components.
The Nilsson Patent discloses a device for mounting circuit components on a circuit board which includes apertures in the plate designed to hold by means of a friction fit.
The Tabuchi Patent discloses an automatic producing apparatus of chip-form electronic parts aggregate. It comprises a tape-like housing body which has a feed hole along the side and a frame type housing hole with a specific pitch between the housing holes.
The Sillner Patent discloses a system for conveying and guiding components, in particular electrical construction elements which are held on a belt in a radially or quasi-radially belted manner. The components are also held by tape at the ends of their leads.
The Higuchi Patent discloses an apparatus for automatically taping electronic components. The electronic components are placed on an elongated tape body at a regular pitch and an adhesive tape is applied to fix the electronic components in position. The electronic component is placed on an elongated first tape and by applying a second tape, the component is fixed between the two tapes.
The Sillner Patent discloses a system for conveying and guiding components, in particular electrical constuction elements which are held on a belt in a radially quasi-radially belted manner. The components in the Sillner Patent are also held by tape at the ends of their leads.
Historically, a solid band of pressure sensitive adhesive (PSA) tape is affixed to a punched plastic carrier tape frame. Integrated circuit (IC) chips on this solid band of PSA tape are sequentially and repeatably placed with the entire back side of each IC chip affixed to and covered by the PSA tape. Such means of adhesive attachment is equivalent to that which is used when the complete wafer from which the IC chips were obtained was prepared and processed for use on an adhesive matrix film mounted in a saw ring or frame. The shear forces encountered during sawing of the silicon wafer to singulate IC chips require 100% adhesion of the wafer to the PSA film to maintain accuracy and integrity of the saw cuts. Once sawn from the wafer and transferred to the adhesive backed carrier tape for storage and transport, individual IC chips are no longer subjected to high level of shear forces. Accordingly, 100% backside surface attachment of each wafer die to a solid band of PSA tape is not required to maintain secure attachment and retention of pre-positioned IC chip orientation. Furthermore, such 100% backside adhesion to the PSA tape is excessive and causes major problems when removing IC chips from the adhesive backed carrier tape. These problems include mispicks during automated high speed assembly placement of IC chips, physical and functional damage to the IC chips, and disorientation of the IC chip as originally placed on the adhesive backing, requiring elaborate positional correction of each IC chip prior to placement with requisite accuracy. The need for properly orienting each IC chip prior to placement is presently obtained by pick and place machines controlled by sophisticated and costly vision systems. Yet a greater cost penalty is experienced by slowing the speed of assembly placement with a resulting loss of throughput.
It is well know to those skilled in the art of singulating IC chips from sawn wafers that such singulation is best accomplished within a few hours after wafers have been sawn. The characteristics of PSA tapes used for sawing result in an increase in adhesion ranging approximately from 5 to 6 times the original adhesion level. Such increase occurs within an approximate two week period of time after sawing of the wafer affixed to PSA film tape which has been separated from a roll and exposed to ambient air. Accordingly, IC chips picked from a sawn wafer on adhesive film which has aged for two or more weeks will be subject to damage, including fracturing and chipping. Stresses in the silicon wafer chips are introduced when high levels of force must be applied to eject the IC chips from the adhesive based wafer during singulation. These stresses are bases for latent defects which are often undetectable during test of assembled circuits, yet cause failures in use after the circuit assemblies have been sold to end user customers.
The aforementioned problems experienced with sawn wafers are perpetuated if a solid band of PSA tape is used to secure IC chips within an adhesive backed carrier tape. Whereas IC chips in sawn wafers are generally picked and singulated within hours after sawing, IC chips placed in adhesive backed carrier tapes arc usually packed, shipped and stored for weeks or months prior to removal at the assembly placement location.
From the foregoing, it is clear that new and improved means are needed to minimize adhesion of IC chips placed in adhesive backed carrier tapes, to enable ready removal during assembly placement of these IC chips by automated means even after many months of storage in carrier tapes prior to assembly use.
An improved method for minimizing adhesion of IC chips within adhesive backed carrier tapes is taught by the '143 Patent which is issued to the inventor and applicant of the present invention. The '143 Patent discloses a split rail configuration of adhesive backing affixed to a punched plastic carrier frame, wherein two parallel strips of PSA tape are utilized in lieu of one solid band of adhesive tape. These two parallel strips of PSA tape are separated by a gap of uniform width which is straddled by the IC chips affixed thereto. In this fashion, only partial surface contact of PSA tape to the back side of each IC chip is made, thus reducing total amount of adhesion and the requisite forces necessary to remove the chip from the adhesive backing.
It has been well demonstrated that adhesion levels needed to retain IC chips in position within adhesive backed carrier tapes and to avoid dislodging these chips during shipment and reeling and dereeling of the adhesive backed carrier tape is about 10% of the adhesion level required to maintain dimensional stability during wafer sawing operations. Exposing only a fraction of the backside of the IC chip to PSA tape when uniformly placed in sites along an adhesive backed carrier tape provides ample adhesion to maintain position of the IC chip on the adhesive backed carrier tape during shipment and storage, and simultaneously permits ready removal of the IC chip from the adhesive backed carrier tape during the assembly placement process.
The '143 Patent teaches that the gap spacing between the two parallel rails of PSA tape may be varied in proportion to chip size to provide optimum levels of adhesion for die of varied sawn dimensions which will span the gap between the two rails of PSA tape. IC chips with the same sawn dimensions are fixed to the two rails of PSA tape, span the gap between PSA tape rails and are positioned so that equal areas of the chip are captured by each rail of PSA tape. Under these conditions, a larger gap between the PSA tape rails will reduce adhesion, whereas a smaller gap will increase adhesion to the PSA tape rails.
In the real world of IC chip making, wafers are designed to maximize the number of IC chips on each wafer and the resulting yield therefrom. Accordingly, there are no industry standards defining sizes of IC chips as bare die, corresponding to the standardized and registered outlines of packages used to contain bare die affixed to lead frames or ball grid arrays, and assembled on printed circuit boards as packaged ICs. In view of the ongoing race for miniaturization in the electronics industry, demanding more features on smaller chips, development of industry standards for IC chip sizes is highly unlikely. As evidenced by molded plastic containers (a.k.a. waffle packs) with a plurality of identically sized cavities to contain IC chips within fixed boundaries, more than five thousand sizes of which are presently cataloged and sold, the sawn dimensions of IC chips vary at random and the variety will continue to increase. Herein lies major cost and inventory problems for packing IC chips in waffle packs and in conventional carrier tapes, both punched and embossed, all of which incorporate cavities of fixed dimensions. Since it is important to restrict free movement of IC chips to avoid damage to these delicate devices during shipment and handling and to provide some semblance of uniform orientation and repeatability in sequencing to enable retrieval by automated assembly machines, an undefinable variety and quantity of IC chip packing mediums with fixed cavity dimensions will be required to accommodate the continued down sizing of IC chip dimensions.
The need for cavities of fixed dimensions to fit each of the multitude of sawn IC chip sizes is eliminated by the adhesive backed carrier tape technology, wherein compartments comprise virtual boundaries, each capable of containing a wide range of IC chip sizes which are securely retained in fixed "as-placed" position by the PSA tape to which each chip is affixed. In the '143 Patent which employs two parallel strips or rails of PSA tape, a total of eight punched carrier tape sizes serve to accommodate chips from the smallest 6 mil to 8 mil transistors and diodes to the largest of the sophisticated microprocessor chips measuring up to 800.times.1400 mils in size. Compared with the market need for many thousands of die carriers containing cavities of fixed size dedicated to a specific chip size, and the cost and inventory problems associated therewith, adhesive backed carrier tape can reduce these problems by three orders of magnitude.
Although compartments in adhesive backed carrier tapes constitute virtual boundaries within which a wide range of IC chip sizes may be placed, a single gap spacing between the two rails of PSA tape may not serve the needs of all of the chip sizes which could be placed within each virtual boundary compartment. To the extent that multiple gap spacings between PSA tape rails are required on same size punched plastic carrier tapes, the versatility and interchangeability of use will be compromised.
Primarily on standardized adhesive backed punched plastic carrier tape frame which comprises 8 mm wide carrier with virtual boundary compartments sized to accommodate chips measuring from approximately nothing to 50 by 110 mils, several different gap spacings between PSA tape rails are utilized and will continue to be required. Adhesive backed carrier tapes containing two rails of PSA tape and intended for use with larger die sizes should require a lesser number of gap space variations, depending upon requirements of assembly placement machines, the tape feeders or de-reelers used in conjunction therewith, and the style and orientation of chips to be placed.
Whereas the technology taught by the '143 Patent to provide two split rails of PSA tape with a gap of controllable width between these PSA tape rails provides means to control adhesion of the chips to the PSA tapes to the minimum needed for secure retention during shipping and handling, thereby enhancing the ability to remove the chips during automated assembly processes without damage, mis-picks, or disorientation, the edges of each strip rail of PSA tape to which chips are attached are defined as straight lines. It has been recognized that straight line edges of the PSA tape rails to which the chips are attached limit variations in adhesion level to only that which can be achieved by varying the gap dimension between the two parallel rails of PSA tape. In addition, it has been recognized that the edges of the two rails of PSA tape to which the chips are affixed can be cut in a variety of configurations--including, but not limited to sawtooth, fringe and sinusoidal patterns, both regular and irregular and that such configuration of PSA tape rail edges can further the benefits of controlling adhesion while simultaneously limiting the quantity and variety of gap spacings required between PSA tape rails, to achieve optimum adhesion of chips. In this context, "optimum adhesion" is defined as that which is just sufficient to secure chips to the adhesive backed carrier tape without dislodgement during shipping, handling or storage of the chips on the carrier tape, thereby allowing chips to be picked from the adhesive backed carrier tape without damage or disorientation.
It is desirable to provide a carrier tape system which includes an adhesive backed punched plastic carrier tape frame having a plurality of aperture cavities which are covered by a solid width of PSA tape affixed to the back side of the carrier tape frame, where the aperture cavities can accommodate a wide range of IC chip sizes within each virtual boundary compartment site within the punched carrier tape frame. It is also desirable to provide a carrier tape system which minimizes adhesion of IC chips placed within each aperture cavity of the punched carrier tape frame to enable ready removal during assembly placement of the IC chips.